Jotego Optimizes Arcade Cores By Killing Unnecessary Wait Cycles

According to a GitHub commit from the JTCPS (Jotego CPS Cores) project, a new update has been pushed to the repository. The change is designed to "prevent refresh cycles from triggering bus wait cycles." It is a single line of logic that represents the kind of obsessive attention to detail required to keep arcade hardware alive in the FPGA era.

Wait, What?

For those of us who do not speak fluent hardware description language, a "wait cycle" is exactly what it sounds like. It is a period where the processor sits idle, twiddling its digital thumbs, waiting for another component (usually memory) to catch up or become available. In vintage hardware, these wait states were often necessary evils dictated by the speed of the RAM chips available at the time.

However, simulating wait states where they do not belong is a problem. The update addresses an issue where memory refresh cycles (the housekeeping tasks that keep DRAM from forgetting its data) were triggering bus wait cycles unnecessarily. By eliminating these false positives, the core ensures that data flows across the virtual bus exactly when it is supposed to, rather than pausing for a ghost in the machine.

The Pursuit of Cycle Accuracy

Jotego is best known for their work on Capcom Play System (CPS) cores, the hardware responsible for bringing us titles like Street Fighter II and Final Fight. When you are dealing with games designed to run on specific 1990s silicon, timing is everything. A delay of a few microseconds here or there can eventually desync audio, glitch graphics, or simply make the game feel "off" to high-level players.

The commit landed on December 24, 2025. Nothing says "dedication to preservation" quite like debugging bus logic on Christmas Eve. It serves as a reminder that while the rest of us are playing the games, engineers are still down in the mines, chipping away at the bedrock of the code to make sure the timing is perfect.